The present invention relates generally to device fabrication, and more particularly to graphene nanoelectronic device fabrication.
Graphene is a crystalline structure of sp2-hybridized carbon bonded together in a honeycomb-like sheet lattice of six-membered rings. Graphene sheets do not readily exist in nature, with graphite being made up of large numbers of graphene sheets layered one on top of another. An individual graphene sheet has a thickness of a single atom, but graphene has only recently been produced or isolated in thicknesses approaching a single sheet. A carbon nanotube may be conceptualized as a nanoscopic segment of a graphene sheet that has been rolled up into a tube shape. Graphene sheets on a nanoscopic or atomic layer scale have the potential for use in a variety of nanoelectronic devices such as field effect transistors, switches, resistors, and interconnects, to name a few. However, while a substantial body of literature exists on the manufacture of carbon nanotubes, experiments for the manufacture of graphene sheets on a nanoscopic or atomic layer scale have generally been conducted using techniques that would be difficult to scale up for commercial application.
For example, one technique to forming graphene is mechanical exfoliation. This technique may be limited because graphene may not be deposited over an entire wafer, and certain coating techniques may produce relatively thick coatings with multiple layers of graphene. Another technique involves thermal decomposition of silicon carbide (SiC) for forming graphene; however, this technique also may not deposit graphene over an entire wafer, and although the thermal decomposition of SiC may be performed with complementary metal oxide semiconductor (CMOS) techniques, the high temperatures needed (e.g., greater than 1400° C.) and the need for a silicon carbide substrate may limit this technique's usefulness beyond basic graphene research.
Some techniques involve chemical reduction of oxidized graphene and chemical intercalation and exfoliation (un-zipping) of multi-walled nanotubes for forming graphene; however, these techniques may produce films where the properties are divergent from mechanical exfoliated or thermally decomposed graphene, and these techniques may not necessarily be conducive with CMOS manufacturing techniques because of the need of non-CMOS compatible chemicals. Another technique for forming graphene is chemical vapor deposition (CVD). This technique for forming graphene may involve the utilization of catalyst materials (e.g., typically thin films of nickel (Ni) or copper (Cu)) and carbonaceous gases. While this technique can readily be implemented into a CMOS foundry, multilayered graphene is often produced, and metal catalyst films may hamper integration into usable devices without further complex process integration.
Thus, there is a need for enhancements to and development of new techniques for the manufacture of graphene sheets on a nanoscopic or atomic layer scale.